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?2005 silicon storage technology, inc. s71150-09-000 1/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit (x8) multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 features: ? organized as 64k x8 / 128k x8 / 256k x8 / 512k x8 ? single voltage read and write operations ? 3.0-3.6v for sst39lf512/010/020/040 ? 2.7-3.6v for sst39vf512/010/020/040 ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 14 mhz) ? active current: 5 ma (typical) ? standby current: 1 a (typical) ? sector-erase capability ? uniform 4 kbyte sectors ? fast read access time: ? 45 ns for sst39lf512/010/020/040 ? 55 ns for sst39lf020/040 ? 70 and 90 ns for sst39vf512/010/020/040 ? latched address and data ? fast erase and byte-program: ? sector-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? chip rewrite time: 1 second (typical) for sst39lf/vf512 2 seconds (typical) for sst39lf/vf010 4 seconds (typical) for sst39lf/vf020 8 seconds (typical) for sst39lf/vf040 ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? 48-ball tfbga (6mm x 8mm) ? 34-ball wfbga (4mm x 6mm) for 1m and 2m ? all non-pb (lead-free) devices are rohs compliant product description the sst39lf512/010/020/040 and sst39vf512/010/ 020/040 are 64k x8, 128k x8, 256k x8 and 5124k x8 cmos multi-purpose flash (mpf) manufactured with sst?s proprietary, high performance cmos superflash technology. the split-gate cell design and thick-oxide tun- neling injector atta in better reliability and manufacturability compared with alternate approaches. the sst39lf512/ 010/020/040 devices write (program or erase) with a 3.0- 3.6v power supply. the sst39vf512/010/020/040 devices write with a 2.7-3.6v power supply. the devices conform to jedec standard pinouts for x8 memories. featuring high performance byte-program, the sst39lf512/010/020/040 and sst39vf512/010/020/ 040 devices provide a maximum byte-program time of 20 sec. these devices use toggle bit or data# polling to indi- cate the completion of program operation. to protect against inadvertent write, they have on-chip hardware and software data protection schemes. designed, manufac- tured, and tested for a wide spectrum of applications, they are offered with a guaranteed typical endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst39lf512/010/020/040 and sst39vf512/010/ 020/040 devices are suited for applications that require convenient and economical updating of program, configu- ration, or data memory. for all system applications, they significantly improves performance and reliability, while low- ering power consumption. they inherently use less energy during erase and program than alternative flash technolo- gies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program oper- ation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet surface mount requirements, the sst39lf512/ 010/020/040 and sst39vf512/010/020/040 devices are offered in 32-lead plcc and 32-lead tsop packages. the sst39lf/vf010 and sst39lf/vf020 are also offered in a 48-ball tfbga package. see figures 1, 2, 3, and 4 for pin assignments. sst39lf/vf512 / 010 / 020 / 0403.0 & 2.7v 512kb / 1mb / 2mb / 4mb (x8) mpf memories
2 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latc hed on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the sst39lf512/010/020/040 and sst39vf512/010/020/040 device is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high imped- ance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 5). byte-program operation the sst39lf512/010/020/040 and sst39vf512/010/ 020/040 are programmed on a byte-by-byte basis. before programming, the sector where the byte exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load byte address and byte data. during the byte-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed, wi thin 20 s. see figures 6 and 7 for we# and ce# controlled program operation timing diagrams and figure 16 for flowcharts. during the program operation, the only valid reads are data# polling and tog- gle bit. during the internal program operation, the host is free to perform additional tasks. any commands written during the internal program operation will be ignored. sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sector architecture is based on uniform sector size of 4 kbyte. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the sector address is latched on the falling edge of the sixth we# pulse, while the command (30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either dat a# polling or toggle bit meth- ods. see figure 10 for timing waveforms. any commands written during the sector-e rase operatio n will be ignored. chip-erase operation the sst39lf512/010/020/040 and sst39vf512/010/ 020/040 devices provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1?s state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte software data protection command sequence with chip-erase command (10h) with address 5555h in the last byte sequence. the internal erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the internal erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 11 for timing diagram, and figure 19 for the flowchart. any commands written during the chip- erase operation will be ignored. write operation status detection the sst39lf512/010/020/040 and sst39vf512/010/ 020/040 devices provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detec- tion includes two status bits: data# polling (dq 7 ) and tog- gle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we# which initiates the internal pro- gram or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid.
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 3 ?2005 silicon storage technology, inc. s71150-09-000 1/06 data# polling (dq 7 ) when the sst39lf512/010/020/040 and sst39vf512/ 010/020/040 are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 for data# polling timing diagram and figure 17 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating ?0?s and ?1?s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector- or chip- erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 9 for toggle bit timing dia- gram and figure 17 for a flowchart. data protection the sst39lf512/010/020/040 and sst39vf512/010/ 020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit t he write operation. th is prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39lf512/010/020/040 and sst39vf512/010/ 020/040 provide the jedec approved software data pro- tection scheme for all data alteration operation, i.e., pro- gram and erase. any program operation requires the inclusion of a series of three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write opera- tions, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte load sequence. these devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid commands w ill abort the device to read mode, within t rc. product identification the product identification mode identifies the devices as the sst39lf/vf512, sst39lf/vf010, sst39lf/vf020 and sst39lf/vf040 and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multi- ple manufacturers in the same socket. for details, see table 4 for software operation, figure 12 for the software id entry and read timing diagram, and figure 18 for the software id entry command sequence flowchart. product identificatio n mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read operation. please note that the software id exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 13 for timing wave- form, and figure 18 for a flowchart. table 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst39lf/vf512 0001h d4h sst39lf/vf010 0001h d5h sst39lf/vf020 0001h d6h sst39lf/vf040 0001h d7h t1.1 1150
4 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 1: p in a ssignments for 32- lead plcc y-decoder i/o buffers and data latches 1150 b1.1 address buffers & latches x-decoder dq 7 - dq 0 memory address oe# ce# we# superflash memory control logic f unctional b lock d iagram 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 nc nc v dd we# nc a12 a15 a16 nc v dd we# nc a12 a15 a16 nc v dd we# a17 a12 a15 a16 a18 v dd we# a17 32-lead plcc top view 1150 32-plcc nh p4.3 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 dq1 dq2 v ss dq3 dq4 dq5 dq6 sst39lf/vf512 sst39lf/vf010 sst39lf/vf020 sst39lf/vf040 sst39lf/vf010 sst39lf/vf020 sst39lf/vf040 sst39lf/vf512 sst39lf/vf512 sst39lf/vf010 sst39lf/vf020 sst39lf/vf040 sst39lf/vf010 sst39lf/vf020 sst39lf/vf040 sst39lf/vf512
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 5 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 2: p in a ssignments for 32- lead tsop (8 mm x 14 mm ) figure 3: p in a ssignment for 48- ball tfbga (6 mm x 8 mm ) for 1 m bit , 2 m bit , and 4 m bit a11 a9 a8 a13 a14 nc we# v dd nc nc a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 nc we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd nc a16 a15 a12 a7 a6 a5 a4 a11 a9 a8 a13 a14 a17 we# v dd a18 a16 a15 a12 a7 a6 a5 a4 sst39lf/vf512 sst39lf/vf010 sst39lf/vf020 sst39lf/vf040 sst39lf/vf010 sst39lf/vf020 sst39lf/vf040 sst39lf/vf512 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1150 32-tsop wh p1.0 standard pinout top view die up 1150 48-tfbga b3k p2.0 a b c d e f g h sst39lf/vf010 6 5 4 3 2 1 top view (balls facing down) a14 a9 we# nc a7 a3 a13 a8 nc nc nc a4 a15 a11 nc nc a6 a2 a16 a12 nc nc a5 a1 nc nc dq5 dq2 dq0 a0 nc a10 nc dq3 nc ce# nc dq6 v dd v dd nc oe# v ss dq7 dq4 nc dq1 v ss 1150 48-tfbga b3k p3.0 a b c d e f g h sst39lf/vf020 6 5 4 3 2 1 top view (balls facing down) a14 a9 we# nc a7 a3 a13 a8 nc nc nc a4 a15 a11 nc nc a6 a2 a16 a12 nc nc a5 a1 a17 nc dq5 dq2 dq0 a0 nc a10 nc dq3 nc ce# nc dq6 v dd v dd nc oe# v ss dq7 dq4 nc dq1 v ss 1150 48-tfbga b3k p4.0 a b c d e f g h sst39lf/vf040 6 5 4 3 2 1 top view (balls facing down) a14 a9 we# nc a7 a3 a13 a8 nc nc a18 a4 a15 a11 nc nc a6 a2 a16 a12 nc nc a5 a1 a17 nc dq5 dq2 dq0 a0 nc a10 nc dq3 nc ce# nc dq6 v dd v dd nc oe# v ss dq7 dq4 nc dq1 v ss
6 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 4: p in a ssignment for 34- ball wfbga (4 mm x 6 mm ) for 1 m bit and 2 m bit table 2: p in d escription symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020, and a 18 for sst39lf/vf040 address inputs to provide memory addresses. during sector-erase a ms -a 12 address lines will select the sector. during block-erase a ms -a 16 address lines will select the block. dq 7 -dq 0 data input/output to ou tput data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply vo ltage: 3.0-3.6v for sst 39lf512/010/020/040 2.7-3.6v for sst39vf512/010/020/040 v ss ground nc no connection unconnected pins. t2.1 1150 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.4 1150 a2 a1 a0 ce# v ss a17 v dd a16 a12 a8 a14 we# a18 a15 a6 a9 a13 a7 a5 a11 a4 nc1 nc2 oe# a3 a10 dq7 a0 a2 ce# dq5 dq3 dq2 dq0 a1 dq6 dq4 v ss dq1 top view (balls facing down) note: for sst39lf020, ball b3 is "no connect" for sst39lf010, balls b3 and a5 are "no connect" a b c d e f g h j 6 5 4 3 2 1 1150 34-wfbga mm p5.0
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 7 ?2005 silicon storage technology, inc. s71150-09-000 1/06 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data byte-program 5555h aah 2aaah 55h 5555h a0h ba 2 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 3 30h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 4,5 5555h aah 2aaah 55h 5555h 90h software id exit 6 xxh f0h software id exit 6 5555h aah 2aaah 55h 5555h f0h t4.2 1150 1. address format a 14 -a 0 (hex), address a 15 can be v il or v ih , but no other value, for the command sequence for sst39lf/vf512. addresses a ms -a 15 can be v il or v ih , but no other value, for the command sequence. a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020, and a 18 for sst39lf/vf040 2. ba = program byte address 3. sa x for sector-erase; uses a ms -a 12 address lines 4. the device does not remain in software product id mode if powered down. 5. with a ms -a 1 = 0; sst manufacturer?s id = bfh, is read with a 0 = 0, sst39lf/vf512 device id = d4h, is read with a 0 = 1, sst39lf/vf010 device id = d5h, is read with a 0 = 1, sst39lf/vf020 device id = d6h, is read with a 0 = 1, sst39lf/vf040 device id = d7h, is read with a 0 = 1. 6. both software id exit operations are equivalent absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. expo- sure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260c for 10 seconds 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange for sst39lf512/010/020/040 range ambient temp v dd commercial 0c to +70c 3.0-3.6v o perating r ange for sst39vf512/010/020/040 range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load c l = 30 pf for sst39lf512/010/020/040 c l = 100 pf for sst39vf512/010/020/040 see figures 14 and 15
8 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 table 5: dc o perating c haracteristics v dd = 3.0-3.6v for sst39lf512/010/020/040 and 2.7-3.6v for sst39vf512/010/020/040 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht , at f=1/t rc min v dd =v dd max read 2 20 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 3 30 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 15 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t5.7 1150 1. typical conditions for the active current shown on the front data sheet page are average values at 25c (room temperature), and v dd = 3v for vf devices. not 100% tested. 2. values are for 70 ns conditions. see the multi-purpose flash power rating application note for further information. 3. 30 ma max for erase operations in the industrial temperature range. table 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t6.1 1150 table 7: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t7.0 1150 table 8: r eliability c haracteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycl e minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t8.3 1150
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 9 ?2005 silicon storage technology, inc. s71150-09-000 1/06 ac characteristics table 9: r ead c ycle t iming p arameters v dd = 3.0-3.6v for sst39lf512/010/020/040 and 2.7-3.6v for sst39vf512/010/020/040 symbol parameter sst39lf512-45 sst39lf010-45 sst39lf020-45 sst39lf040-45 sst39lf020-55 sst39lf040-55 sst39vf512-70 sst39vf010-70 sst39vf020-70 sst39vf040-70 units min max min max min max t rc read cycle time 45 55 70 ns t ce chip enable access time 45 55 70 ns t aa address access time 45 55 70 ns t oe output enable access time 30 30 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 0 0 ns t olz 1 oe# low to active output 0 0 0 ns t chz 1 ce# high to high-z output 15 15 25 ns t ohz 1 oe# high to high-z output 15 15 25 ns t oh 1 output hold from address change 000 ns t9.2 1150 table 10: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp byte-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 40 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t sce chip-erase 100 ms t10.1 1150
10 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 5: r ead c ycle t iming d iagram figure 6: we# c ontrolled p rogram c ycle t iming d iagram 1150 f03.0 address a ms-0 dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020 and a 18 for sst39lf/vf040 1150 f04.0 address a ms-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020 and a 18 for sst39lf/vf040
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 11 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 7: ce# c ontrolled p rogram c ycle t iming d iagram figure 8: d ata # p olling t iming d iagram 1150 f05.0 address a ms-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020 and a 18 for sst39lf/vf040 1150 f06.0 address a ms-0 dq 7 dd# d# d we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020 and a 18 for sst39lf/vf040
12 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 9: t oggle b it t iming d iagram figure 10: we# c ontrolled s ector -e rase t iming d iagram 1150 f07.0 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020 and a 18 for sst39lf/vf040 1150 f08.0 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minmum timings are met. (see table 10) sa x = sector address a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020, and a 18 for sst39lf/vf040
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 13 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 11: we# c ontrolled c hip -e rase t iming d iagram figure 12: s oftware id e ntry and r ead 1150 f17.0 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minmum timings are met. (see table 10) a ms = most significant address a ms = a 15 for sst39lf/vf512, a 16 for sst39lf/vf010, a 17 for sst39lf/vf020, and a 18 for sst39lf/vf040 1150 f09.2 note: device id = d4h for sst39lf/vf512, d5h for sst39lf/vf010, d6h for sst39lf/vf020, and d7h for sst39lf/vf040. address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa bf device id 55 aa 90
14 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 13: s oftware id e xit and r eset 1150 f10.0 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 15 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 14: ac i nput /o utput r eference w aveforms figure 15: a t est l oad e xample 1150 f12.1 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1150 f11.1 to tester to dut c l
16 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 16: b yte -p rogram a lgorithm 1150 f13.1 start load data: aah address: 5555h load data: 55h address: 2aaah load data: a0h address: 5555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 17 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 17: w ait o ptions 1150 f14.0 wait t bp , t sce, or t se byte-program/ erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 byte-program/ erase initiated byte-program/ erase initiated
18 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 18: s oftware id c ommand f lowcharts 1150 f15.2 load data: aah address: 5555h software id entry command sequence load data: 55h address: 2aaah load data: 90h address: 5555h wait t ida read software id load data: aah address: 5555h software id exit & reset command sequence load data: 55h address: 2aaah load data: f0h address: 5555h load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 19 ?2005 silicon storage technology, inc. s71150-09-000 1/06 figure 19: e rase c ommand s equence 1150 f16.1 load data: aah address: 5555h chip-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 10h address: 5555h load data: aah address: 5555h wait t sce chip erased to ffh load data: aah address: 5555h sector-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 30h address: sa x load data: aah address: 5555h wait t se sector erased to ffh
20 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 product ordering information environmental attribute e 1 = non-pb package modifier h = 32 leads k = 48 balls m = 34 balls (54 possible positions) package type b3 = tfbga (0.8mm pitch, 6mm x 8mm) n = plcc m = wfbga (0.5mm pitch, 4mm x 6mm) w = tsop (type 1, die up, 8mm x 14mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 45 = 45 ns 55 = 55 ns 70 = 70 ns device density 040 = 4 mbit 020 = 2 mbit 010 = 1 mbit 512 = 512 kbit voltag e l = 3.0-3.6v v = 2.7-3.6v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are rohs compliant. sst 39 lf 040 - 45 - 4c - nh e xx x x xxx x - xxx -xx - xxx x
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 21 ?2005 silicon storage technology, inc. s71150-09-000 1/06 valid combinations for sst39lf512 sst39lf512-45-4c-nh sst39lf512-45-4c-wh sst39lf512-45-4c-nhe sst39lf512-45-4c-whe valid combinations for sst39vf512 sst39vf512-70-4c-nh sst39vf512-70-4c-wh sst39vf512-70-4c-nhe sst39vf512-70-4c-whe sst39vf512-70-4i-nh sst39vf512-70-4i-wh sst39vf512-70-4i-nhe sst39vf512-70-4i-whe valid combinations for sst39lf010 sst39lf010-45-4c-nh sst39lf010-45-4c-wh sst39lf010-45-4c-b3k sst39lf010-45-4c-mm sst39lf010-45-4c-nhe sst39lf010-45-4c-whe sst39lf010-45-4c-b3ke sst39lf010-45-4c-mme valid combinations for sst39vf010 sst39vf010-70-4c-nh sst39vf010-70-4c-wh sst39vf010-70-4c-b3k sst39vf010-70-4c-nhe sst39vf010-70-4c-whe sst39vf010-70-4c-b3ke sst39vf010-70-4i-nh sst39vf010-70-4i-wh SST39VF010-70-4I-B3K sst39vf010-70-4i-nhe sst39vf010-70-4i-whe SST39VF010-70-4I-B3Ke valid combinations for sst39lf020 sst39lf020-45-4c-nh sst39lf020-45-4c-wh sst39lf020-45-4c-b3k sst39lf020-45-4c-mm sst39lf020-45-4c-nhe sst39lf020-45-4c-whe sst39lf020-45-4c-b3ke sst39lf020-45-4c-mme sst39lf020-55-4c-nh sst39lf020-55-4c-wh sst39lf020-55-4c-nhe sst39lf020-55-4c-whe valid combinations for sst39vf020 sst39vf020-70-4c-nh sst39vf020-70-4c-wh sst39vf020-70-4c-b3k sst39vf020-70-4c-nhe sst39vf020-70-4c-whe sst39vf020-70-4c-b3ke sst39vf020-70-4i-nh sst39vf020-70-4i-wh sst39vf020-70-4i-b3k sst39vf020-70-4i-nhe sst39vf020-70-4i-whe sst39vf020-70-4i-b3ke valid combinations for sst39lf040 sst39lf040-45-4c-nh sst39lf040-45-4c-wh sst39lf040-45-4c-nhe sst39lf040-45-4c-whe sst39lf040-45-4c-b3ke sst39lf040-55-4c-nh sst39lf040-55-4c-wh sst39lf040-55-4c-nhe sst39lf040-55-4c-whe valid combinations for sst39vf040 sst39vf040-70-4c-nh sst39vf040-70-4c-wh sst39vf040-70-4c-nhe sst39vf040-70-4c-whe sst39vf040-70-4c-b3ke sst39vf040-70-4i-nh sst39vf040-70-4i-wh sst39vf040-70-4i-nhe sst39vf040-70-4i-whe sst39vf040-70-4i-b3ke note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations.
22 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 packaging diagrams 32- lead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh 48- ball t hin - profile , f ine - pitch b all g rid a rray (tfbga) 6 mm x 8 mm sst p ackage c ode : b3k .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30? a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 23 ?2005 silicon storage technology, inc. s71150-09-000 1/06 32- lead t hin s mall o utline p ackage (tsop) 8 mm x 14 mm sst p ackage c ode : wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0?- 5? detail
24 data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 ?2005 silicon storage technology, inc. s71150-09-000 1/06 34- ball v ery - very - thin - profile , f ine - pitch b all g rid a rray (wfbga) 4 mm x 6 mm sst p ackage c ode : mm j h g f e d c b a abcdefghj 6 5 4 3 2 1 6 5 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.32 0.05 (34x) a1 indicator 4 6.00 0.08 2.50 4.00 a1 corner top view 34-wfbga-mm-4x6-32mic-1 note: 1. although many dimensions are similar to those of jedec publication 95, mo-225, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. no ball is present in position a1; a gold-colored indicator is present. 5. ball opening size is 0.29 mm ( 0.05 mm) 1mm detail side view seating plane 0.20 0.06 0.63 0.10 0.08
data sheet 512 kbit / 1 mbit / 2 mbit / 4 mbit multi-purpose flash sst39lf512 / sst39lf010 / sst39lf020 / sst39lf040 sst39vf512 / sst39vf010 / sst39vf020 / sst39vf040 25 ?2005 silicon storage technology, inc. s71150-09-000 1/06 table 11: r evision h istory number description date 01 ? 2000 data book feb 2000 02 ? changed speed from 45 ns to 55 ns for the sst39lf020 and sst39lf040 aug 2000 03 ? 2002 data book: reintroduced the 45 ns parts for the sst39lf020 and sst39lf040 feb 2002 04 ? added the b3k package for the 2 mbit devices ? added footnote in table 5 to indicate i dd write is 30 ma max for erase operations in the industrial temperature range. oct 2002 05 ? changes to table 5 on page 8 ? added footnote for mpf power usage and typical conditions ? clarified the test conditions for power supply current and read parameters ? clarified i dd write to be program and erase ? corrected i dd program and erase from 20 ma to 30 ma ? part number changes - see page 21 for additional information mar 2003 06 ? added new ?mm? micro-package mpns for 1m and 2m lf parts- see page 21 oct 2003 07 ? 2004 data book ? added non-pb mpns and removed footnote (see page 21) ? updated b3k and mm package diagrams nov 2003 08 ? added rohs compliant statement. ? added 4 mbit to figure 3. ? revised absolute max stress ratings for surface mount solder reflow temperature ? removed sst39vfxxx-90 timing parameters from figure 9. ? added footnote and removed read access speed 90 = 90 to product ordering infor- mation. ? removed 90 part numbers valid combinations lists dec 2005 09 ? edited page valid combinations on page 21. changed 39lf040-70-4c-b3ke to 39lf040-45-4c-b3ke jan 2006 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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